Description

The RDS-TCB Tail-Circuit Buffer is designed to provide selectable bi-directional buffering between two data circuits that are operating at nominally the same clock rate and are capable of providing clocking as a DCE. In such cases, the timing of the two circuits is not locked to the same timing source, or may be allowed to deviate from a com-mon timing source for a length of time. The RDS-TCB meets this need by pro-viding selectable amounts of bi-directional memory from 1,024 bits up to 8,192 bits and supports synchronous clock rates up to 2.048 Mbps.

The data memory is based upon a self-centering FIFO buffer. Upon power-on, a reset, or a prior buffer underrun or over-flow, the buffer will accept and hold all input data until the buffer is half full. At that point, the buffer will be released to output the first data received and will continue input and output through the FIFO at the rate determined by the input and output clocks. Differences in clock-ing rates on the two interfaces will result in the amount of data queued in the buffer changing over time. As long as the amount queued does not decrease to zero (FIFO empty) or reach the maxi-mum memory value selected (FIFO full), then data output will correctly match data input, with a delay that is a function of the length of the queue and the bit clock rate.

An additional option controls whether certain control signals, namely DCD on the input side to RTS on the output side, are passed directly through the buffer without delay, or through the buffer memory with the same delay as data.

The RDS-TCB is housed in a sturdy metal standalone or Rackmount enclo-sure and operates on 110/220VAC.

The unit has a three-year warranty and a 24-hour turnaround on warranty repairs.