Description

The RDS-SB is a device intended to provide a unidirectional 2.097 Mbit elastic data buffering (FIFO memory) function between two systems having nominally equivalent clocking rates. The two systems may be either running asynchronously, or may be traceable to a common timing source while one or both systems may possess a high degree of clock jitter.
The RDS-SB provides two DTE interfaces optionally configured as RS-449, X.21, EIA-530, or V.35. The maximum data transfer rate at each interface is 2.048 Mbps.
An option switch on the front panel allows the RDS-SB internal buffer memory to utilize a Differential Frequency Discriminator to prevent the FIFO memory from re-centering after an underrun or overflow until the frequency difference between the two external clocks is within a set range.
Data buffering is provided from the Receive Data (RD) input lead of Port A through the FIFO memory to the Send Data (SD) output lead of Port B. Data input on Port A is sampled on the clock edge occurring at the center of the data bit time period. Data output on Port B is latched on the clock edge occurring at the beginning of the data bit time period.


The 2.097 Mb First-In, First-out (FIFO) memory is used to buffer data in and out of the unit. Receive data may be simultaneously written into the FIFO while transmit data is read out. Internal counters track the FIFO level and are used to indicate underrun and overflow conditions, as well as indicate when the FIFO is half-full (centered) after initialization.
After a power-on cycle, or an underrun or overflow condition, the state of the FIFO is reset to an initial empty state, whereupon it will begin to accept input data at the Port A clock rate while inhibiting the output of data. Upon reaching a half-full (re-centered) state, the FIFO is enable to clock data out at the Port B clock rate.
A Differential Frequency Discriminator (DFD) may be invoked to conditionally hold off accepting received data and re-centering the FIFO after a power-on cycle, or an underrun or overflow condition occurs, until the frequency difference between the two port clocks falls within a set range of approximately 400 Hz. The purpose of this function is to prevent an out of range clocking source from repeatedly producing frequent underrun or overflow conditions.
When this function is invoked, and only after an underrun or overflow condition occurs, the FIFO memory is held in an initial state of empty if the DFD indicates that the absolute frequency differential is outside the range. If at any time within the sample window of the DFD (approx. 20mS), this differential should fall within the range, the FIFO will re-center normally and begin transferring data. (NOTE: It is possible in some cases that the average frequency differential will be outside the range, but may at times fall within the range due to clock jitter. This will be sufficient to trigger re-centering of the FIFO and transfer of data.)
The output of the DFD will be ignored as long as the FIFO continues to transfer data without an underrun or overflow condition occurring.
The RDS-SB is housed in a sturdy metal enclosure and operates on 110/220VAC.

The unit has a three year warranty and a 24 hour turnaround on warranty repairs.